; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=X64 define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind { ; X32-LABEL: test_broadcast_2f64_4f64: ; X32: ## BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: vmovaps (%eax), %xmm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_broadcast_2f64_4f64: ; X64: ## BB#0: ; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = load <2 x double>, <2 x double> *%p %2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> ret <4 x double> %2 } define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind { ; X32-LABEL: test_broadcast_2i64_4i64: ; X32: ## BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: vmovaps (%eax), %xmm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_broadcast_2i64_4i64: ; X64: ## BB#0: ; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = load <2 x i64>, <2 x i64> *%p %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> ret <4 x i64> %2 } define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind { ; X32-LABEL: test_broadcast_4f32_8f32: ; X32: ## BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: vmovaps (%eax), %xmm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_broadcast_4f32_8f32: ; X64: ## BB#0: ; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = load <4 x float>, <4 x float> *%p %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> ret <8 x float> %2 } define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind { ; X32-LABEL: test_broadcast_4i32_8i32: ; X32: ## BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: vmovaps (%eax), %xmm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_broadcast_4i32_8i32: ; X64: ## BB#0: ; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = load <4 x i32>, <4 x i32> *%p %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> ret <8 x i32> %2 } define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind { ; X32-LABEL: test_broadcast_8i16_16i16: ; X32: ## BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: vmovaps (%eax), %xmm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_broadcast_8i16_16i16: ; X64: ## BB#0: ; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = load <8 x i16>, <8 x i16> *%p %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> ret <16 x i16> %2 } define <32 x i8> @test_broadcast_16i8_32i7(<16 x i8> *%p) nounwind { ; X32-LABEL: test_broadcast_16i8_32i7: ; X32: ## BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: vmovaps (%eax), %xmm0 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_broadcast_16i8_32i7: ; X64: ## BB#0: ; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = load <16 x i8>, <16 x i8> *%p %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> ret <32 x i8> %2 }